Job Details

Overview

Technical Lead Manager, Silicon Product Development, Google Cloud – Sunnyvale, CA, USA

Advanced: Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

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Google is an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, or any other basis protected by law.

The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for Google services and Google Cloud. We prioritize security, efficiency, and reliability across everything we do, from developing TPUs to running a global network, shaping the future of hyperscale computing and supporting Google Cloud's Vertex AI and Gemini initiatives.

The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Salary ranges are determined by role, level, and location. Individual pay within the range is based on location and factors including job-related skills, experience, and education or training. Salary details reflect base salary; bonus, equity, and benefits are provided separately. Learn more about benefits at Google.

Responsibilities

• Lead Post Silicon Engineering Activities from DFT requirements, including New Product Introduction (NPI), System Level testing, and HVM (including Yields analysis and Return Merchandise Authorization (RMA)/Failure Analysis (FA).
• Lead a team to develop silicon product test hardware and software, silicon data analytics, and system level testing.
• Work closely with NPI-HVM team on manufacturing management, tracking, quality, and cost optimization.
• Develop a robust NPI team to facilitate the execution of multiple products. Prioritize the creation of a systematic NPI Test Program strategy that includes clear definition, efficient execution, and ongoing refinement.
• Build and track high performance IC test and characterization flows for PVT, signal and power integrity characterization, system correlation, and participate in silicon debug, Electrical Failure Analysis (EFA), and Physical Failure Analysis (PFA).

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in IC product development or test engineering, and manufacturing (characterization, qualification, bring-up, yield improvement, and debug).
• 6 years of experience in people management, developing employees.
• Experience building test programs and HVM floor engineering support/management.
• Experience working with vendors.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in wafer probe card, ATE hardware, and managing suppliers on execution of test hardware development and bring-up.
• Experience in test engineering, DFT, test hardware, and test program development (e.g., Teradyne UltraFlex, Advantest 93k platforms).
• Experience in programming/scripting (e.g., C and C++, Python, or Perl).
• Knowledge of probability and statistical fundamentals for data analysis and process control design.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a focus on TPU architecture and its integration within AI/ML-driven systems.

As a Silicon Operation Engineering Manager, you will build high quality manufacturing flow and take it to High Volume Manufacturing (HVM). You will define, lead, and track our products operation covering HVM, NPI, ATE Test and Characterization, System level Testing, Burn In, Cost reduction and Yield improvements processes. You will deliver products in the fabless semiconductor model with deep knowledge covering the full manufacturing flow including High volume production, fab, test, DFT, package assembly, and qualification.

You will be managing a team responsible for developing test programs and hardware for wafer probe and the ATE (Automated Testing Equipment) for characterization and production testing of very high performance networking and machine learning ICs. You will utilize ATE equipment tools and capabilities to optimize final test programs without compromising quality. You will also be responsible for developing test plans and supporting the full life cycle of the product from design to volume manufacturing till end of life.

The Google MSCA organization designs, implements, and manages hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Our end users are Googlers, Cloud customers, and billions of people who use Google services worldwide.

Google is committed to security, efficiency, and reliability across everything we do, including TPUs and hyperscale computing.

Google is a global company and English proficiency is a requirement for all roles unless stated otherwise in the job posting.